In accordance with an exemplary scenario, a delay line set is capable of providing a fixed delay (e.g., a programmable delay) independent of voltage, temperature and/or process variations. The delay line set utilizes a reference (e.g., a reference clock) to calibrate and ensure the fixed delay. Some exemplary delay line sets include one or more delay lines connected or coupled with one another in series. Each of the delay lines from among a plurality of delay lines has an input and an output such that an input signal applied at an input node produces a delayed signal at the output of each delay of these delay lines. Each of the delay lines includes one or more delay paths. Each delay path from among a plurality of delay paths may include zero or more delay elements. Examples of the delay elements may include, for example, buffers, flip flops, logic gates, and the like. Each delay path from among a plurality of delay paths is configurable to produce a predetermined delay based on zero or more delay steps. Each delay path from among a plurality of delay paths provides an intrinsic delay corresponding to zero, or a minimum number of, delay steps. The intrinsic delay may be, for example, a minimum delay contributed by each delay path independent of a number of delay steps.
Moreover, an exemplary scenario provides that, in applications such as de-skewing, clock-centering, and clock balancing, the fixed delays are configured or implemented to ensure maximized margins. Some exemplary delay lines can be configured to provide a fixed delay of either ¼th or ⅕th of a reference clock period by modeling the clock period in four or five delay elements, respectively. However, in applications such as de-skewing in circuits, fixed delays that are different than ¼th or ⅕th the reference clock period may be implemented. In some exemplary scenarios, the above-mentioned issues may be mitigated by using computer-implemented techniques to configure each delay line so as to produce a plurality of delays that are different than ¼th or ⅕th the reference clock period. However, such computer-implemented techniques may involve a significant amount of computationally intensive data processing, software and hardware support. Moreover, such computer-implemented techniques may also involve engaging a dedicated processor for the above-mentioned purposes.